P4 is a language for programming the data plane of network devices. From p4.org web site:
«P4 is a domain-specific programming language for specifying the behaviour of the dataplanes of network-forwarding elements. »
This 1st article exposes:
- A brief introduction to the P4 language
- A basic P4 development workflow
- Some basic specificities of the P4 language
This article is preliminary a pure introduction to P4lang P4. It does not correspond in any way to an extensive programming language description nor a P4 compilation guide.
Diagram: P4 development workflow
[ #001 ] - Cookbook: P4 development workflow
Based on what we mentioned, what does the "P4 Domain specific language" give you ? Concretely:
- You can write a program as you would in C or C++ but you'd have to follow the P4 language specification. (The current one is P4_16, there is also a previous P4_14 specification.)
- That program is compiled with a p4 compiler in P4_16 or P4_14 (similar to C++14/C++11)
- The resulting compilation artifacts can be then loaded into an equipment implementing a P4 model commonly called a P4 target that is able to interpret/run p4 binaries. Here we will be using BMv2, a softwarized P4 target intended for learning.
The specificities are:
- This P4 program is YOUR program
- This P4 program allows you to define the YOUR OWN packet processing logic
In short, you can now program:
«how a packet that comes into your system, is processed and goes out your system»
Diagram packet processing description
The diagram above depicts 2 perspectives:
- P4 program development workflow
- It starts by writing your P4 program using your favorite editor
- compile your program with the P4 compiler of your target
- load your program into the P4 target
- my_program.p4 packet progressing logic: "all packets arriving at port 4 are switched/forwarded to port 8"
- In this example, the switch has 8 ports
- A ingress packet arrives at port 4
- the ingress port is then checked
- If it is port 4, then the packet is switched to port 8
- my_program.p4 does not implement a default condition, so all the packets not arriving on port 4 are then dropped
- the ingress packets arrived with a header with charateristics set by the previous node
- if needed, my_program.p4 is able to set modify the egress packet header for further processing by the next network node (example of in-band network Telemetry)
Router for Academia Research & Education (RARE) & P4
The RARE project objective is to provide a networking solution to Research & Education institution use cases. While we witnessed the birth of several control plane such as GNU Zebra, Bird, exaBGP, etc. The common point of these softwares is that they don't have the capability (yet) to be coupled easily with a hardware dataplane. Simply put, these software control plane cannot be used without specific/important development in order to run on an equipment able to forward nx100GE links at a high Mpps rate.
There have been attempts with DPDK and other kernel bypass mechanism, that enabled higher throughput processing capability, but this is not comparable to commercial/vendor equipment's packet processing power.
- opens you the door to software AND hardware dataplane programmability
- gives you the possibility to implement YOUR own packet processing algorithm
RARE control plane: freeRouter
In the RARE project, we are using a software control plane called freeRouter:
- It is an open source control plane
- It has been deployed since 2014 and benefits from hours of production in various environment
- Interworking has been extensively and continuously tested with major equipment vendors
- Last but not least freeRouter's maintainer is in the RARE team which allowed Rapid Application development and prototyping in order to build control plane and P4 dataplane communication.
P4 use cases are mostly inherently linked to the P4 target you plan to use in order to run your P4 program:
A comprehensive list can be found here.
- P4Lang BMv2 V1Model target:
It is the P4Lang virtual model that emulates a PISA architecture. You can run it on a VM and start writing your first P4 program and load it on simple_switch and/or simple_switch_grpc (if you plan to use P4Runtime). While this is a great solution in order to learn P4 and sketch your packet processing algorithm, it is not recommended for production use.
- INTEL/BAREFOOT TOFINO/TOFINO 2
This target also implements a PISA architecture and proposes a Virtual model so that you can validate your algorithm. However, once validated on the virtual model, you can load your program into a hardware switch that is running a NPU called TOFINO and its bigger brother TOFINO2. While TOFINO is able to handle 6.4 Tbps of traffic rate, TOFINO2 simply doubles this. (12 Tbps) In addition to that, TOFINO2 exposes additional inherent capabilities like bigger buffer, memory and TCAM compared to his little brother.
These are the use cases enabled by the combination of P4 and RARE software:
- Service Provider core router:
You can build a robust packet switching fabric at the scale of Telecom Service Provider able to switch packets at n×100GE
- Service Provider edge router:
You can build an edge router an Interconnect the core router above. These routers will terminate your backbone network service like L2/L3 plain IP or VPN services (IPv4 - IPv6)
- Datacenter ToR switch
With the WEDGE100BF32X you can have 2x100GE uplinks toward 2 distinct "leaf switches", it leaves you 30x100GE server connections.
- Datacenter Spine/Leaf switch
The WEDGE100BF32X is also a good candidate router in DC as a core/spine switch. You can create a fabric able to switch 6.4 Tbps trafic rates
- Internet Exchange
In this case, the WEDGE100BF32X is 100GE a peer aggregator or simply integrated into the IXP distributed core fabric.
- MAN/CPE router
The STORDIS BF2556X-1T with its flexible connectivity options is a good candidate for regional network implementation. It has 8x100GE ports, 2 of them can be used as uplinks toward their main transit provider, 2 other can be used to provide EAST/WEST connection via 2 different fire routes, this leave 4x100 ports in case you need to increase capacity. The STORDIS also has 16x[1/10/25] GbE ports, 32x[10/25] GbE ports which gives the possibility to interconnects users via various access port bandwidth.
In this article you:
- had a brief introduction of P4Lang P4 language
- had been presented a 10 thousand feet view of P4 development workflow
- had been exposed a list of P4 targets and the use cases enabled by these targets
P4Lang P4 for dummy [ #001 ] - key take-away
__THE__ exciting INNOVATION provided by P4 boils down into this community language that unlocks and opens for you the door of system's dataplane. Till now, dataplane programming was reserved to commercial vendors. Some of these dataplanes like the well known CEF (Cisco Express Forwarding) are specific to Cisco equipment. Juniper, has its own dataplane (not sure about the name) implemented by Forwarding Plane component. (example of vMX architecture)
P4 language inherent characteristics:
- Behavioral programming language
- Language with constraints
- Limited number of variable types
- With fixed size
- P4 is not a general purpose language, You cannot program any software. like C, C++ or Java
It is therefore a simple language, that is easier to be tamed by network managers rather than pure software developers. Indeed, writing a P4 program is all about defining the behavior of a network packet processing algorithm based on intrinsic variables encoded into the packet header.